1/7 AN1686 application note march 2003 introduction purpose of this note is to provide a few brief design guidelines on the switch-mode power supply whose elec- trical specification is summarized in the following table. table 1. design electrical specification the special requirement for this converter is the ability to cope with a peak power demand from the load that exceeds the maximum continuous power by over 66% for a limited time ( 0.5 s), still maintaining output voltage regulation, and to automatically shut down in case this overload lasts more than a specified time. furthermore, symbol parameter value unit v in input voltage range 88 to 264 v acrms f l mains frequency 50/60 hz p outx maximum continuous output power 45 w p outpk peak output power (t 0.5 s) (*) 75 w v out regulated output voltage (@ p out =0 ? p outpk , v in = 88 ? 264 v ac ) 18v 2% v d v out output voltage ripple (@p out = p outx , v in =88 ? 264 v ac )2% f osc normal operation switching frequency 70 khz f sb light load switching frequency 18 khz h target efficiency (@p out = p outx , v in =88 ? 264 v ac ) 80 % maximum input power (@p out = 0.5 w, v in =88 ? 264 v ac ) 2w maximum input power (open load, v in =88 ? 264 v ac ) 1w notes: (*) if p out is such that p outx < p out p outpk the converter shall be shutdown (latch mode) within 1 ? 2 s; a load exceeding p outpk shall cause converters shutdown (latch mode) within 10 ? 100 ms. by c. adragna an l5991-based converter with temporary extra power capability in some applications the smps, normally supposed to deliver a certain amount of power, from time to time undergoes load peaks that can be even two or more times as much. such peaks are often too long to be properly handled by oversizing the output capacitors, but short if compared to the thermal time constants of the power components. typical examples of such loads are motors and audio systems. in this case, designing the smps for the peak power demand from the load would lead to a poorly used and more expensive system. it is more cost-effective to design for the maximum continuous power and allow the peak power to pass. however, if for any reason the load demands such peak power level for a long time, some of the power components, not sized for withstanding this, will definitely fail unless the system is stopped somehow. in this application note a design example of such a system, based on the st's advanced pwm control- ler l5991, is carried out.
AN1686 application note 2/7 in case of anomalous power demand from the load (exceeding the peak power, e.g. due to a short circuit), con- verter's shutdown must occur within 10 ? 100 ms. a power peak lasting 0.5 s is too long to be handled with just a reinforced output capacitor bank: as a matter of fact, after few ms the converter's control loop has already reacted to maintain the output voltage regulated. thus a power demand lasting 0.5 s can be considered as a steady-state operating condition from the electrical point of view. on the other hand the thermal time constants of the power components are such that the heat gener- ated during a power peak of even a couple of seconds will not cause an excessive temperature rise: their ther- mal impedance is to be invoked rather than their thermal resistance . from these considerations, it turns out that the converter can be thermally designed just considering the maxi- mum continuous output power p outx (and the related rms currents) that it has to deliver and not the peak power demand p outpk . there are, however some points that one should consider for the electrical design: 1) the overcurrent limiting circuit must allow p outpk to pass, hence its setpoint needs to be greater than the cor- responding peak primary current ip pklim and, possibly, much greater than the peak primary current related to p outx ; 2) the transformer and/or inductor must not saturate with this higher peak current; 3) there is a tradeoff between the input bulk capacitor size (which determines the minimum input dc voltage) and the value of ip pklim : a low capacitance leads to a high input voltage ripple, then to a lower minimum input dc voltage and to a higher ip pklim . also the maximum duty cycle of the converter must account for the re- sulting minimum dc input voltage. 4) as envisaged by the spec in table 1, designing the converter for a given power but allowing a much higher level calls for a means to make the system work safely during abnormal operating conditions. except for the special requirement discussed so far, the specification is identical to that of the converter consid- ered in [1], which will be then used as the starting point for the present design. in this context, only the modifi- cations needed for fully complying with the spec of table 1 will be discussed. for reader's convenience figure 1 reproduces the electrical schematic of the original converter. additional circuitry will be needed for discriminating a peak power demand from a normal load condition and detecting a short circuit as well as realizing the required double time-out. figure 1. 45w, wide-range mains ac-dc adapter: electrical schematic (original design) 88 to 264 vac bd1 df04m c1 100 f 400 v r1 56 k w 10 r11 10 w 13 r14 1 k w 15 12 r15 0.47 w 1/2 w 8 14 6 r6 330 k w 43 2 r9 6.8 k w c5 3.3 nf r13 8.2 k w 7 q1 stp7nb60 c9 330 f 25 v gnd ic1 l5991 c12 4.7 nf 1kv d2 stta106 r7 4.7 w r5 47 k w c2 47 f 25 v r10 22 w 5 9 dcc r8 5.6 k w vref c4 100 nf c6 56 nf rct ss dc-lim sgnd r3 2.2 m w c8 100 pf 11 pgnd isen out vc vcc dis comp vfb t1 vout 16 st-by 7 6 1 2 4 3 r19 1.2 k w r17 4.3 k w r21 348 w c7 220 pf c3 100 nf c14 470 nf r12 24 k w r16 100 w r18 2.2 k w r20 5.6 k w d4 1n4148 d5 byw29-200 r2 56 k w r4 2.2 m w c10 330 f 25 v c11 330 f 25 v ic2 pc917 n1 n2 n3 f1 t2a250v d3 1n4148 ntc1 r22 c17 c13 c15 100 nf j1 j2 d1 bzw06-154
3/7 AN1686 application note adaptations and modifications of the original design with reference to the schematic of figure 1, here follows a step-by-step discussion on the modifications needed for fulfilling the spec of table 1. input capacitor. looking at the evaluation results presented in [1], it is reasonable to assume that with 75 w load the input power will be around 90 w. estimating about 5 w power loss before the transformer, the power managed by the transformer will be 85 w. with the worst-case spread (-20 %) of c1, that is with c1=80 f, the valley voltage across c1 is expected to be around 54 v. under these conditions the maximum peak primary current will be around 3.24a, exceeding the saturation current of the transformer (2.84a). moreover, the maximum duty cycle (@ vin = 54v) will be around 59%: since the system is working in ccm, slope compensation will be needed to avoid unconditional instability of the current loop and the resulting sub- harmonic oscillations. to avoid remaking the transformer and adding the slope compensation circuit, an attempt can be done using a larger c1. assuming there is no change in power levels, with 150 f capacitance (120 f, worst case), the val- ley voltage across c1 will be 78 v, the maximum peak primary current 2.88 a and the maximum duty cycle 50%. although necessary, this step is not enough to guarantee that the transformer will not saturate and then the sys- tem is still very close to the instability limit. the transformer needs then to be modified anyway (see the following points). sense resistor. the sense resistor r15 needs reducing, to allow a peak primary current of 2.88 a. the maximum value should be 0.92 v / 2.88 a = 0.319 w . this will be achieved by paralleling a 1 w resistor (1%, metallic film) to the existing 0.47 w . the worst-case peak current, will be 1.08 v / 0.319 w = 3.39 a. transformer. the changes to the transformer aim at meeting two specific requirements: 1) not to saturate with 3.39a primary current; 2) to reduce the maximum duty cycle below 50%, to avoid the use of a slope compen- sation circuit. design constraint is the core size, which must be unchanged. the increase of total losses should be as low as possible. starting from point 2), to maintain the same maximum duty cycle as in the original design, the turn ratio should be reduced proportionally to the reduction of the valley voltage across c1. formerly, with 45 w load, the worst- case valley voltage was 83 v and now is 78 v, then the new turn ratio is (50/12)(78/83) = 3.916. table 2. modified transformer specification to make sure that the core will not saturate with 3.39a, keeping the same inductance value, the number of turns of the primary winding should be raised from 50 to 66 and the air gap from 0.7 to 1.5 mm. to reduce the copper, it is acceptable to reduce the primary inductance by 10%: in this way the primary winding turn number will be 60 and the air gap 1.4 mm. the secondary turn number will be 60/3.916=15.321, rounded off to 16. keeping the same wire diameters, the primary resistance will be increased by a factor 60/50, that is 20%, and the secondary resistance by 33% and so will be the respective conduction losses (the rms currents change very little). however, the flux swing is core philips efd30x15x9, 3c85 material or equivalent bobbin horizontal mounting, 12 pins air gap ? 1.4 mm for an inductance 2-6 of 360 h leakage inductance < 10 h windings spec & build winding wire s-f turns notes pri1 awg27 2-4 30 sec (a) awg25 11-7 16 bifilar with sec (b) sec (b) awg25 12-8 16 bifilar with sec (a) pri2 awg27 4-6 30 aux awg32 3-1 14 evenly spaced note: sec (a) and sec (b) are paralleled on the pcb
AN1686 application note 4/7 reduced by 18%, which means that the core losses will be reduced by about 38%. the estimated total loss in- crease is only 0.1 w, hence the hot-spot temperature increase (as compared to the original design) should be under 3 c. it is then not necessary to change the wire size. the specification of the modified transformer is summarized in table 2. table 3. list of modifications to the original design input voltage compensation. r3 and r4 compensate for the internal propagation delay of the pwm block to achieve an actual overcurrent setpoint independent of the input voltage. their value is directly proportional to the sense resistor r15 and inversely to the primary inductance. since both parameters are changed r3 and r4 needs adjustment. the new value for each of them will be 2.2 m w (0.319/0.47)(400/360)=1.6 m w . table 3 summarizes all of the modifications described in this paragraph. circuit for delayed shutdown upon overpower/short circuit the objective of the circuit of figure 2 is to provide a double programmable delay before shutting down the l5991 following on either an overload (a longer delay) or a short circuit (a shorter delay). figure 2. circuit for delayed shutdown upon overpower/short circuit: electrical schematic r23 and r24 define a voltage threshold, which the output of the e/a (comp) will be compared to. if the l5991 is running at normal frequency, that is, the pin st-by is internally connected to the 5v reference vref, q2 is on and the voltage at pin 2 of the lm393 is: (1) if the l5991 is running at low frequency (because of a light load) the pin st-by is floating and, being connected to the oscillator through a resistor [2], oscillates between 1 and 3 v, well below the threshold of the zener d6. q2 is then off and v2 equals vref, hence the voltage at pin comp, v(comp), cannot exceed v2 as long as part original value new value note c1 100 f 150 f r15 0.47 w 0.319 w = (0.47 w // 1 w ) same power rating t1 see [1] see table 2 r2, r3 2.2 m w 1.6 m w same power rating 4 vref d7 1n4148 7 dis + - + - comp 8 2 3 1 6 5 ic3a lm393 ic3b lm393 q1 bc327 r23 10 k w r24 24 k w r25 4.3 k w r26 100 k w r27 22 k w c18 10 f st-by q2 bc337 d6 4v7 r28 3.3 k w v2 vref r24 r23 r24 + ---------------------------- - =
5/7 AN1686 application note the converter is in regulation (p out p outpk ). this is to avoid any interference with the standby function: with a light load and the l5991 running at the lower frequency, v(comp) might be greater then the value of v2 defined by (1), thus triggering the delayed shutdown function erroneously. assuming q2 is on, when v(comp) > v2 the output of ic3a (which is open-collector) goes high and c18 is charged through r26. the time needed for c18 to be charged at v2 is: when this voltage is reached, the output of ic3b goes high and the voltage at pin dis of the l5991 is pulled above 2.5v, thus causing a latched shutdown of the pwm controller and of the converter too. the converter will stay idle as long as it is supplied by the input power source. to be able to restart the system, the power source must be removed. the diode d7 is used because the pin dis is already biased (by a resistor divider to set up ovp protection) so as to decouple the two circuits. note that if the condition v(comp) > v2 disappears (i.e. p out falls below p outx ) before td1 has elapsed, the output of ic3a goes back low thus discharging c18 and stopping this slow shutdown countdown. in case of short circuit comp will saturate high and tend to go over 6 v. in that case not only the output of ic3b will go high but also q1 will be turned on (v(comp) will be clamped at about 5.6v), thus c18 will be charged through r25 and r26. this circuit is analogous to that shown in [3]. the delay will be approximately: , since r25 is selected << r26, so that td 2 << td 1 . note, if v(comp) goes back to the regulation region (i.e. p out falls below p outpk ) before td 2 has elapsed, the charge of c18 through r25 will be stopped; the slow charge through r26 can be stopped too or still go on, de- pending on whether v(comp) has fallen below v2 (p out < p outx ) or not. one more comment: comp is saturated high and q1 turned on (initiating the fast shutdown countdown) every time the converter is started up, during the ramp-up of the output voltage from zero to the regulated value. ob- viously, td 2 needs to be greater than this time (usually, 520 ms) or the converter will never start. with the part values shown in fig. 2, the results are the following: refer to the appendix of [4] for formulae useful for relating the voltage level on pin comp to the power level in a flyback converter, to be able to design the circuit under different conditions. figure 3 shows how the circuit of figure 2 is inserted into the modified 45w demo board (the changes are high- lighted by the shaded regions) and the oscilloscope pictures of figure 4 illustrate the experimental results in case of both overload and short circuit. if converter's latched shutdown is not desired, but the user wants the system to automatically recover normal operation when the overload/short is removed, yet maintaining a low power throughput during the fault, it is very easy to modify the circuit of figure 2 to achieve this: r27 will be reduced at 2.2 k w and the diode d7 connected to the isen pin of the l5991, so as to invoke its "hiccup" ocp [2]. the resulting schematic is illustrated in figure 5, its insertion into the 45w ac-dc adapter is obvious. td 1 r26 c18 vref vref v2 C ------------------------------ - ?? ?? ln = td 2 r25 c18 vref vref v2 C ------------------------------ - ?? ?? ln ? v2 5 24 10 24 + ------------------- 3.53v == td 1 100 10 3 10 10 6 C 5 53.53 C -------------------- - ?? ?? ln 13.4 () ln 1.22s === td 2 4.3 10 3 10 10 6 C 5 53.53 C -------------------- - ?? ?? ln 4.3 10 2 C 3.4 () ln 52ms ===
AN1686 application note 6/7 figure 3. electrical schematic of the modified 45w ac-dc adapter inclusive of the circuit of figure 2 figure 4. timings of the circuit in figure 2: a) overload (iout = 4 a); b) short circuit 88 to 264 vac bd1 df04m c1 150 f 400 v r1 56 k w 10 r11 10 w 13 r14 1 k w 15 12 r15 0.47 w 1/2 w 8 14 6 r6 330 k w 43 2 r9 6.8 k w c5 3.3 nf r13 8.2 k w 7 q1 stp7nb60 c9 330 f 25 v gnd ic1 l5991 c12 4.7 nf y2 d2 stta106 r7 4.7 w r5 47 k w c2 47 f 25 v r10 22 w 5 9 dcc r8 5.6 k w vref c4 100 nf c6 56 nf rct ss dc-lim sgnd r3 1.6 m w w w w c8 100 pf 11 pgnd isen out vc vcc dis comp vfb t1 18v/2.5a (4.2 a pk) 16 st-by 7 6 1 2 4 3 r19 1.2 k w r17 4.3 k w r21 348 w c7 220 pf c3 100 nf c14 470 nf r12 24 k w r16 100 w r18 2.2 k w r20 5.6 k w d4 1n4148 d5 byw29-200 r2 56 k w r4 1.6 m w w w w c10 330 f 25 v c11 330 f 25 v ic2 pc917 n1 n2 n3 f1 t2a250v d3 1n4148 ntc1 r24 r22 c17 c13 c15 100 nf d1 bzw06-154 4 d7 1n4148 7 + - + - 8 2 3 1 6 5 ic3a lm393 ic3b lm393 q1 bc327 r23 10 k w r24 24 k w r25 4.3 k w r26 100 k w r27 22 k w c1 10 f q2 bc337 d6 4v7 r28 3.3 k w r15a 1 w 1/4 w v comp timing (pin 5 lm393) disable (pin 7 lm393) v out v comp timing (pin 5 lm393) disable (pin 7 lm393) v out a) b) overload detection threshold overload short circuit
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 7/7 AN1686 application note figure 5. circuit of figure 2 modified for autorecovery mode operation in case of activation, the converter will be stopped and restarted after a delay set by the ss capacitor of the l5991 (c6). if this delay is long enough, the vcc capacitor (c2) may be discharged below the uvlo threshold of the l5991, giving origin to even longer delays. references [1] "45 w ac-dc adapter with standby function" (an1134) [2] "l5991 primary controller with standby" datasheet [3] "how to handle short circuit conditions with st's advanced pwm controllers" (an1215) [4] "minimize power losses of lightly loaded flyback converters with the l5991 pwm controller" (an1049) 4 vref d7 1n4148 7 isen + - + - comp 8 2 3 1 6 5 ic3a lm393 ic3b lm393 q1 bc327 r23 10 k w r24 24 k w r25 4.3 k w r26 100 k w r27 2.2 k w c18 10 f st-by q2 bc337 d6 4v7 r28 3.3 k w
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